Field of the Invention
The present invention relates to a power transmitting apparatus and a method for controlling the same.
Description of the Related Art
In recent years, a wireless power transmission technique has been widely researched and developed. With this technique, power transmission efficiency decreases due to variation in power consumed by loads (hereinafter referred to as “load variation”) and variation in distance between transmitting and receiving apparatuses (e.g., variation in distance between antennas. Hereinafter referred to as “gap variation”) (Takehiro Imura et al, “Experimental Analysis of High Efficiency Power Transfer using Resonance of Magnetic Antennas for the Near Field”, Proceedings of the IEE-Japan Industry Applications Society Conference II, August 2008, p. 539-542). Also, a technique of using a class E amplifier as a power transmitting apparatus has been developed as well (Japanese Patent Laid-Open No. 2012-146289). An example of the configuration of a class E amplifier 106 is shown in FIG. 2. The class E amplifier 106 is constituted by an N-channel MOSFET 200 (hereinafter referred to as “FET 200”), two inductors, and two capacitors. Also, the class E amplifier 106 includes a gate 201, a drain 202, and a source 203 in the FET 200 as terminals. The class E amplifier 106 switches a supplied DC voltage (hereinafter referred to as “Vdd”) 204 using a pulse that is input to the gate 201, and converts it to an AC voltage.
The voltage waveform in the periphery of the FET 200 in the case where the class E amplifier 106 is applied to a power transmission system will be described next with reference to FIG. 4. FIG. 4 is a diagram showing variation over time in the voltage waveforms in the periphery of the FET 200, although the details thereof will be described in an embodiment. In FIG. 4, a dotted chain line 400 is the waveform of the voltage between the gate 201 and the source 203 (hereinafter referred to as “Vgs”). According to the dotted chain line 400, the FET 200 transitions to an off state at time T0 and is in the off state in the period from time T0 to time T1. Then, the FET 200 transitions to an on state at time T1. A double-dotted chain line 401 is the waveform of the voltage between the drain 202 and the source 203 when the class E amplifier 106 performs an ideal operation (hereinafter referred to as “Vds”). According to the double-dotted chain line 401, the Vds at time T1 when the FET 200 transitions to the on state is 0 Volts, and the slope of the Vds is also 0. Here, “slope” means a value obtained by differentiating the change in the Vds with respect to time.
Thus, the class E amplifier 106 causes the Vds to resonate in the period when the FET 200 is in the off state (from time T0 to time T1). Also, ideally, the FET 200 transitions to the on state when the Vds is 0 Volts, and the slope of the Vds is 0 (hereinafter referred to as “zero voltage switching”). This reduces switching loss and enables high-efficiency power conversion. Also, the output setting value (hereinafter referred to as the “setting value”) of the class E amplifier 106 can be set by increasing or reducing the Vdd 204, and if the Vdd 204 is increased, the setting value is increased. Note that the times T1 written in the present description all indicate the time when the FET 200 transitions to the on state.
The voltage waveforms in the periphery of the FET 200 in the case where load variation or gap variation occurs will be described next with reference to FIG. 6. FIG. 6 is a diagram showing variation over time in the voltage waveforms in the periphery of the FET 200 in the case where load variation or gap variation occurs, although the details thereof will be described in the embodiments. A dotted line 601 is an example of the Vds waveform in the case where load variation or gap variation occurs. According to the dotted line 601, at time T1, the Vds is not 0 Volts, and the slope of the Vds is not 0. At this time, switching loss occurs in the FET 200 and efficiency decreases. Accordingly, it is necessary to resolve the problem of reduced efficiency that is caused by switching loss in the FET 200 if load variation or gap variation occurs.